Design of Efficient Low Power Stable 4-Bit Memory Cell
نویسندگان
چکیده
منابع مشابه
Design of Efficient Low Power Stable 4-Bit Memory Cell
The power consumption and speed of SRAMs are important issue that has led to multiple designs with the purpose of minimizing the power consumption during both read and write operations. Memory is the furthermost collective part in CMOS IC’s applications. Here a novel 9T static random access memory (SRAM) cell design which consumes less dynamic power and has high read stability is predicted. Thi...
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Multiplication is a basic operation in any signal processing application. Multiplication is the most important one among the four arithmetic operations like addition, subtraction, and division. Multipliers are usually hardware intensive, and the main parameters of concern are high speed, low cost, and less VLSI area. The propagation time and power consumption in the multiplier are always high. ...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2013
ISSN: 0975-8887
DOI: 10.5120/14539-2614